A Keynote Presentation at COOL Chips 25, April 20-22, 2022

Our Processor Development Engineer, Shotaro Shintani will have a keynote presentation at COOL Chips 25 held at Takeda Hall, The University of Tokyo, Japan at April 20-22, 2022.
This symoposium will also be held online.

Registration here

[ Tittle ]
RISC-V-based parallel processor IP with vector extension for embedded systems

[ Abstract ]
There are a variety of controls in automobiles, and the amount of processing is continuously on the increase due to the more complex algorithms. Moreover, the progress of autonomous driving has been remarkable in recent years, and the performance requirements have increased dramatically in addition to the diversification of processing. There are also traditional requirements in automotive systems, such as hard real-time performance, functional safety, power efficiency, software portability, and so on. On the other hand, there is the problem that software development will become more complex and less portable when several processors or accelerators are adopted to meet the automotive requirements.

In order to solve it, we develop new processors with enough performance and flexibility in a single architecture that can handle the various types of processing for autonomous driving while also satisfying the traditional automotive requirements such as functional safety.

In this presentation, our first-generation Data Flow Processor (DFP), DR1000C, is introduced, and it is targeted at safety-critical systems and delivers the real-time performance and high-throughput data processing required for microcontrollers for embedded systems. DR1000C is a RISC-V-based multiple instruction stream, multiple data stream (MIMD) processor with a vector processing unit. It also supports a hardware multi-threading mechanism that allows up to 16 threads which simultaneously share the vector processing unit, resulting in highly efficient resource use. Furthermore, DR1000C has the necessary functional safety modules and meets ISO 26262 ASIL B to D safety requirements without additional external special safety mechanisms.

Our evaluation results show that DR1000C can efficiently process control algorithms such as Model Predictive Control (MPC). DR1000C is also the world’s first RISC-V processor with vector extensions which has achieved ISO 26262 ASIL D Ready certification. Lastly, our product roadmap and portfolio are referred to for addressing the area of autonomous driving, which is the target of the next-generation DFP.