CadenceLIVE Americas 2021に登壇

2021年6月8日(火), 6月9日(水)(注)にオンラインで開催されるCadenceLIVE Americas 2021にて、
弊社Senior Hardware Engineerの大久保 直昭が、DR1000Cプロセッサの開発期間短縮を実現した



タイトル : Rapid RISC-V Automotive Processor IP Development Accelerated by Cadence Digital Full Flow

概要 :
In commercial processor IP development, quick PPA optimization is an essential task for launching high-quality and high-performance IPs to the market.
Cadence Digital Full Flow provides a seamless connection between tools, enabling designers to focus on architecture exploration and optimization.
Thanks to the usability of the flow, front-end engineers can join a floorplan exploration. It realizes rapid front-end to back-end iterative optimization to tailor the IP design across process libraries and PPA targets.
In this presentation, we will look at how the flow contributed to our RISC-V processor IP development, highlighting Joules RTL power estimation and Genus Synthesis from architecture exploration to implementation,
and how adding Stratus High-Level Synthesis allowed us to develop a NN accelerator without modifying RTL code.