Our Senior Hardware Engineer, Naoaki Okubo, will be speaking at CadenceLIVE Americas 2021 on June 8-9(*), 2021.
At this event, he will talk about how we developed our multi-thread vector processor(DFP DR1000C)
and achieved the best performance within the tight design deadline by fully utilizing Cadence EDA tools.
(*): PDT(Pacific Daylight Time)
Title : Rapid RISC-V Automotive Processor IP Development Accelerated by Cadence Digital Full Flow
In commercial processor IP development, quick PPA optimization is an essential task for launching high-quality and high-performance IPs to the market.
Cadence Digital Full Flow provides a seamless connection between tools, enabling designers to focus on architecture exploration and optimization.
Thanks to the usability of the flow, front-end engineers can join a floorplan exploration.
It realizes rapid front-end to back-end iterative optimization to tailor the IP design across process libraries and PPA targets.
In this presentation, we will look at how the flow contributed to our RISC-V processor IP development,
highlighting Joules RTL power estimation and Genus Synthesis from architecture exploration to implementation,
and how adding Stratus High-Level Synthesis allowed us to develop a NN accelerator without modifying RTL code.