RISC-V Global Forum

We are now the silver sponser of RISC-V Grobal Forum held in September 3, 2020. Sugimoto, CTO and Adachi, CPU Architect have speaker session, "Vector Compliance Testing for RISC-V" at 5:45pm(JST)/8:45am(UTC) , which will also feature on our processor IP : DR1000C that we used Imperas Vector Compliance Test Suite to develop. See detail followings About our presentation About RISC-V Global Forum
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NSITEXE Adopts Synopsys HAPS Prototyping to Validate Data Flow Processor IP

NSITEXE Accelerates Customer Engagements Using High-Performance HAPS Solution MOUNTAIN VIEW, Calif., Aug. 19, 2020 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) today announced that NSITEXE adopted Synopsys HAPS®-80 prototyping solution to develop their current and next-generation Data Flow Processor (DFP) IP portfolio. See detail here
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Granted “Joint research and development of a compiler backend for Secure Open Architecture and the design and development of a supported runtime environment”, commissioned by NEDO

Granted "Joint research and development of a compiler backend for Secure Open Architecture and the design and development of a supported runtime environment", commissioned by NEDO ---- Research and development of OS and development tools for RISC-V core, a rapidly growing open processor IP, and establishment of a ecosystem with domestic vendors ----   NSITEXE, Inc. (Head Office: Minato-k...
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